The present invention relates in general to communication systems, and is particularly directed to reduced complexity matched filter architecture having its temporal length subdivided into cascaded sub-symbol filter segments, the number of sub-symbol segments is selected to prevent loss of an unacceptable amount of signal energy over received signal frequency uncertainty xcex4f. The sub-symbol filter segments are processed in plural phase rotation-signal combiner stages, outputs of which are associated with multiple frequency bins, the number of which is a trade-off between desired granularity and cost. A respective phase rotation-signal combiner stage multiplies sub-symbol filter segments by respectively offset phase rotation vectors, associated with the plural frequency bins. The sub-symbol phase vector products of each stage are summed to produce plural frequency bin outputs.
A frequent requirement of portable wireless devices (e.g., pagers or tag-embedded transponders for object tracking) is that the transmitter be small, inexpensive and battery-powered. This dictates using relatively low cost components that not only transmit a signal at a relatively low power level but inherently have relatively xe2x80x98sloppyxe2x80x99 tolerances that result in a large frequency uncertainty xcex4f. Often the only effective means to realize a useful communication range is to transmit relatively long (e.g., low data rate spread spectrum) symbols, so as to increase the total energy per symbol to an acceptable level. At a receiver site, this mandates processing each symbol in a coherent fashion in order to fully exploit its energy. Unfortunately, the frequency uncertainty xcex4f is often too high relative to the symbol rate Rs to allow conventional matched filter processing. Indeed, FIG. 1, which shows the implementation loss of coherent signal processing as a function of the xcex4f/Rs ratio, reveals unacceptable recovered energy degradation when the xcex4f/Rs ratio exceeds+/xe2x88x920.5 cycles per symbol. This frequency uncertainty problem has often been corrected at the receiver by xe2x80x98tuningxe2x80x99 the receiver""s signal processing mechanism to what was received.
As diagrammatically illustrated in FIG. 2, this typically involves adjusting a local oscillator 11, whose output is multiplied in a mixer 12 by a received signal 13 for application to a downstream matched filter 15. Where tuning a single local oscillator is infeasible, for example where the transmitted signal is of relatively short duration (e.g., bursty) or multiple signals are transmitted simultaneously (as in the case of multiple pagers or tag transponders, referenced above), the receiver""s processing circuitry may be replicated multiple times, as shown in FIG. 3, using a plurality of respectively different local oscillators LO1, LO2, LO3, LO4, . . . , LOM to ensure that one of the plurality of local oscillatorxe2x80x94mixerxe2x80x94matched filter processing paths 12-1/15-1, . . . , 12-N/15-M (frequency bins) will produce an output signal having an acceptable xcex4f/Rs ratio. Unfortunately, this matched filter circuitry replication approach necessarily substantially increases the complexity and cost of the receiver processor.
In accordance with the present invention, the above discussed frequency uncertainty problem is successfully addressed by a new and improved xe2x80x98sub-symbolxe2x80x99 matched filter architecture, that subdivides the matched filter into a plurality of successive (cascaded) sub-symbol filter segments MF1, MF2, MF3, . . . MFN. Each sub-symbol filter segment has a duration Ts/N (where Ts is the overall temporal span of the matched filter). The segment duration Ts/N is short enough to avoid the loss of an unacceptable amount of signal energy over the frequency uncertainty xcex4f that would otherwise prevent recovery of the transmitted signal.
Each sub-symbol matched filter segment MFi is applied to a plurality K of phase rotation-signal combiner stages S1, S2, S3, . . . SK, the outputs of which are associated with K frequency bins. A respective phase rotation-signal combiner stage Si contains a plurality of N multipliers that are operative to multiply the outputs of the sub-symbol filter segments by a set of respectively offset phase rotation vectors. The sets of offset N phase rotation vectors of each of the phase rotation-signal combiner stages differ from one another, in association with the K frequency bins. The N sub-symbol phase vector products of a respective jth stage are summed to produce a respective one of the K frequency bin outputs.
The number K (of frequency bins) is a trade-off between the desired granularity of the filter and cost, while the number N (of sub-symbol segments) is selected to prevent loss of an unacceptable amount of signal energy over the frequency uncertainty xcex4f. The sub-symbol segmented matched filter processor facilitates implementing the multiple frequency bin paths of FIG. 3 by means of only a single matched filter data register, and replicating the same signal combiner circuitry for each of the plurality of K frequency bins. By quantizing the sub-symbols""phase rotations to readily implementable digital signal processing values, such as integral multiples of xcfx80/2 (90xc2x0), the circuit complexity of the phase rotation multipliers is reduced to direct and inverted connections between a respective sub-symbol segment and a single adder. This enables plural frequency bins for relatively long symbols to be processed on a single integrated circuit chip.